ANDN
Logical AND NOT
| Opcode/Instruction | Op/En | 64/32-bit Mode | CPUID Feature Flag | Description |
|---|---|---|---|---|
| VEX.LZ.0F38.W0 F2 /r ANDN r32a, r32b, r/m32 | RVM | V/V | BMI1 | Bitwise AND of inverted r32b with r/m32, store result in r32a. |
| VEX.LZ. 0F38.W1 F2 /r ANDN r64a, r64b, r/m64 | RVM | V/N.E. | BMI1 | Bitwise AND of inverted r64b with r/m64, store result in r64a. |
Instruction Operand Encoding
| Op/En | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
| RVM | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the
second source operand). The result is stored in the first operand (destination operand).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
DEST := (NOT SRC1) bitwiseAND SRC2;
SF := DEST[OperandSize -1];
ZF := (DEST = 0);
Flags Affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-29, “Type 13 Class Exception Conditions.”
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be incomplete or broken in various obvious or non-obvious ways. Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious.