CMPPD
Compare Packed Double Precision Floating
| Opcode/Instruction | Op / En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| 66 0F C2 /r ib CMPPD xmm1, xmm2/m128, imm8 | A | V/V | SSE2 | Compare packed double precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate. |
| VEX.128.66.0F.WIG C2 /r ib VCMPPD xmm1, xmm2, xmm3/m128, imm8 | B | V/V | AVX | Compare packed double precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate. |
| VEX.256.66.0F.WIG C2 /r ib VCMPPD ymm1, ymm2, ymm3/m256, imm8 | B | V/V | AVX | Compare packed double precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate. |
| EVEX.128.66.0F.W1 C2 /r ib VCMPPD k1 {k2}, xmm2, xmm3/m128/m64bcst, imm8 | C | V/V | AVX512VL AVX512F | Compare packed double precision floating-point values in xmm3/m128/m64bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.256.66.0F.W1 C2 /r ib VCMPPD k1 {k2}, ymm2, ymm3/m256/m64bcst, imm8 | C | V/V | AVX512VL AVX512F | Compare packed double precision floating-point values in ymm3/m256/m64bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
| EVEX.512.66.0F.W1 C2 /r ib VCMPPD k1 {k2}, zmm2, zmm3/m512/m64bcst{sae}, imm8 | C | V/V | AVX512F | Compare packed double precision floating-point values in zmm3/m512/m64bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. |
Instruction Operand Encoding
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (r, w) | ModRM:r/m (r) | imm8 | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | imm8 |
| C | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | imm8 |
Description
Performs a SIMD compare of the packed double precision floating-point values in the second source operand and the first source operand and returns the result of the comparison to the destination operand. The comparison predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in the two source operands.
EVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand (first operand) is an opmask register. Comparison results are written to the destination operand under the writemask k2. Each comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false).
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source operand (third operand) can be a YMM register or a 256-bit memory location. The destination operand (first operand) is a YMM register. Four comparisons are performed with results written to the destination operand. The result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The second source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAXVL-1:128) of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with results written to bits 127:0 of the destination operand. The result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the destination ZMM register are zeroed. Two comparisons are performed with results written to bits 127:0 of the destination operand.
The comparison predicate operand is an 8-bit immediate:
- For instructions encoded using the VEX or EVEX prefix, bits 4:0 define the type of comparison to be performed (see Table 3-1). Bits 5 through 7 of the immediate are reserved.
- For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
| Predicate | imm8 Value | Description | Result: A Is 1st Operand, B Is 2nd Operand | Signals #IA on QNAN | |||
|---|---|---|---|---|---|---|---|
| A >B | A<B | A=B | Unordered1 | ||||
| EQ_OQ (EQ) | 0H | Equal (ordered, non-signaling) | False | False | True | False | No |
| LT_OS (LT) | 1H | Less-than (ordered, signaling) | False | True | False | False | Yes |
| LE_OS (LE) | 2H | Less-than-or-equal (ordered, signaling) | False | True | True | False | Yes |
| UNORD_Q (UNORD) | 3H | Unordered (non-signaling) | False | False | False | True | No |
| NEQ_UQ (NEQ) | 4H | Not-equal (unordered, non-signaling) | True | True | False | True | No |
| NLT_US (NLT) | 5H | Not-less-than (unordered, signaling) | True | False | True | True | Yes |
| NLE_US (NLE) | 6H | Not-less-than-or-equal (unordered, signaling) | True | False | False | True | Yes |
| ORD_Q (ORD) | 7H | Ordered (non-signaling) | True | True | True | False | No |
| EQ_UQ | 8H | Equal (unordered, non-signaling) | False | False | True | True | No |
| NGE_US (NGE) | 9H | Not-greater-than-or-equal (unordered, signaling) | False | True | False | True | Yes |
| NGT_US (NGT) | AH | Not-greater-than (unordered, signaling) | False | True | True | True | Yes |
| FALSE_OQ(FALSE) | BH | False (ordered, non-signaling) | False | False | False | False | No |
| NEQ_OQ | CH | Not-equal (ordered, non-signaling) | True | True | False | False | No |
| GE_OS (GE) | DH | Greater-than-or-equal (ordered, signaling) | True | False | True | False | Yes |
| GT_OS (GT) | EH | Greater-than (ordered, signaling) | True | False | False | False | Yes |
| TRUE_UQ(TRUE) | FH | True (unordered, non-signaling) | True | True | True | True | No |
| EQ_OS | 10H | Equal (ordered, signaling) | False | False | True | False | Yes |
| LT_OQ | 11H | Less-than (ordered, nonsignaling) | False | True | False | False | No |
| LE_OQ | 12H | Less-than-or-equal (ordered, nonsignaling) | False | True | True | False | No |
| UNORD_S | 13H | Unordered (signaling) | False | False | False | True | Yes |
| NEQ_US | 14H | Not-equal (unordered, signaling) | True | True | False | True | Yes |
| NLT_UQ | 15H | Not-less-than (unordered, nonsignaling) | True | False | True | True | No |
| NLE_UQ | 16H | Not-less-than-or-equal (unordered, nonsignaling) | True | False | False | True | No |
| ORD_S | 17H | Ordered (signaling) | True | True | True | False | Yes |
| EQ_US | 18H | Equal (unordered, signaling) | False | False | True | True | Yes |
| NGE_UQ | 19H | Not-greater-than-or-equal (unordered, non-signaling) | False | True | False | True | No |
| NGT_UQ | 1AH | Not-greater-than (unordered, nonsignaling) | False | True | True | True | No |
| FALSE_OS | 1BH | False (ordered, signaling) | False | False | False | False | Yes |
| NEQ_OS | 1CH | Not-equal (ordered, signaling) | True | True | False | False | Yes |
| GE_OQ | 1DH | Greater-than-or-equal (ordered, nonsignaling) | True | False | True | False | No |
| GT_OQ | 1EH | Greater-than (ordered, nonsignaling) | True | False | False | False | No |
| TRUE_US | 1FH | True (unordered, signaling) | True | True | True | True | Yes |
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions
- If either operand A or B is a NAN.
The unordered relationship is true when at least one of the two source operands being compared is a NaN; the ordered relationship is true when neither source operand is a NaN.
A subsequent computational instruction that uses the mask result in the destination operand as an input operand will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds to a QNaN.
Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison) or by using software emulation. When using software emulation, the program must swap the operands (copying registers when necessary to protect the data that will now be in the destination), and then perform the compare using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7 (Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A) under the heading Emulation.
Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand CMPPD instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-2. The compiler should treat reserved imm8 values as illegal syntax.
| Pseudo-Op | CMPPD Implementation |
|---|---|
| CMPEQPD xmm1, xmm2 | CMPPD xmm1, xmm2, 0 |
| CMPLTPD xmm1, xmm2 | CMPPD xmm1, xmm2, 1 |
| CMPLEPD xmm1, xmm2 | CMPPD xmm1, xmm2, 2 |
| CMPUNORDPD xmm1, xmm2 | CMPPD xmm1, xmm2, 3 |
| CMPNEQPD xmm1, xmm2 | CMPPD xmm1, xmm2, 4 |
| CMPNLTPD xmm1, xmm2 | CMPPD xmm1, xmm2, 5 |
| CMPNLEPD xmm1, xmm2 | CMPPD xmm1, xmm2, 6 |
| CMPORDPD xmm1, xmm2 | CMPPD xmm1, xmm2, 7 |
Table 3-2. Pseudo-Op and CMPPD Implementation
The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-3, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand pseudo-ops in addition to the four-operand VCMPPD instruction. See Table 3-3, where the notations of reg1 reg2, and reg3 represent either XMM registers or YMM registers. The compiler should treat reserved imm8 values as
illegal syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPD instructions in a similar fashion by extending the syntax listed in Table 3-3.
| Pseudo-Op | CMPPD Implementation |
|---|---|
| VCMPEQPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0 |
| VCMPLTPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1 |
| VCMPLEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 2 |
| VCMPUNORDPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 3 |
| VCMPNEQPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 4 |
| VCMPNLTPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 5 |
| VCMPNLEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 6 |
| VCMPORDPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 7 |
| VCMPEQUQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 8 |
| VCMPNGEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 9 |
| VCMPNGTPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0AH |
| VCMPFALSEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0BH |
| VCMPNEQOQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0CH |
| VCMPGEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0DH |
| VCMPGTPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0EH |
| VCMPTRUEPD reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 0FH |
| VCMPEQOSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 10H |
| VCMPLTOQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 11H |
| VCMPLEOQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 12H |
| VCMPUNORDSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 13H |
| VCMPNEQUSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 14H |
| VCMPNLTUQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 15H |
| VCMPNLEUQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 16H |
| VCMPORDSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 17H |
| VCMPEQUSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 18H |
| VCMPNGEUQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 19H |
| VCMPNGTUQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1AH |
| VCMPFALSEOSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1BH |
| VCMPNEQOSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1CH |
| VCMPGEOQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1DH |
| VCMPGTOQPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1EH |
| VCMPTRUEUSPD _reg1, reg2, reg3 | VCMPPD reg1, reg2, reg3, 1FH |
Table 3-3. Pseudo-Op and VCMPPD Implementation
Operation
CASE (COMPARISON PREDICATE) OF
0: OP3 := EQ_OQ; OP5 := EQ_OQ;
1: OP3 := LT_OS; OP5 := LT_OS;
2: OP3 := LE_OS; OP5 := LE_OS;
3: OP3 := UNORD_Q; OP5 := UNORD_Q;
4: OP3 := NEQ_UQ; OP5 := NEQ_UQ;
5: OP3 := NLT_US; OP5 := NLT_US;
6: OP3 := NLE_US; OP5 := NLE_US;
7: OP3 := ORD_Q; OP5 := ORD_Q;
8: OP5 := EQ_UQ;
9: OP5 := NGE_US;
10: OP5 := NGT_US;
11: OP5 := FALSE_OQ;
12: OP5 := NEQ_OQ;
13: OP5 := GE_OS;
14: OP5 := GT_OS;
15: OP5 := TRUE_UQ;
16: OP5 := EQ_OS;
17: OP5 := LT_OQ;
18: OP5 := LE_OQ;
19: OP5 := UNORD_S;
20: OP5 := NEQ_US;
21: OP5 := NLT_UQ;
22: OP5 := NLE_UQ;
23: OP5 := ORD_S;
24: OP5 := EQ_US;
25: OP5 := NGE_UQ;
26: OP5 := NGT_UQ;
27: OP5 := FALSE_OS;
28: OP5 := NEQ_OS;
29: OP5 := GE_OQ;
30: OP5 := GT_OQ;
31: OP5 := TRUE_US;
DEFAULT: Reserved;
ESAC;
VCMPPD (EVEX Encoded Versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
CMP := SRC1[i+63:i] OP5 SRC2[63:0]
ELSE
CMP := SRC1[i+63:i] OP5 SRC2[i+63:i]
FI;
IF CMP = TRUE
THEN DEST[j] := 1;
ELSE DEST[j] := 0; FI;
ELSE DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VCMPPD (VEX.256 Encoded Version)
CMP0 := SRC1[63:0] OP5 SRC2[63:0];
CMP1 := SRC1[127:64] OP5 SRC2[127:64];
CMP2 := SRC1[191:128] OP5 SRC2[191:128];
CMP3 := SRC1[255:192] OP5 SRC2[255:192];
IF CMP0 = TRUE
THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] := 0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] := 0000000000000000H; FI;
IF CMP2 = TRUE
THEN DEST[191:128] := FFFFFFFFFFFFFFFFH;
ELSE DEST[191:128] := 0000000000000000H; FI;
IF CMP3 = TRUE
THEN DEST[255:192] := FFFFFFFFFFFFFFFFH;
ELSE DEST[255:192] := 0000000000000000H; FI;
DEST[MAXVL-1:256] := 0
VCMPPD (VEX.128 Encoded Version)
CMP0 := SRC1[63:0] OP5 SRC2[63:0];
CMP1 := SRC1[127:64] OP5 SRC2[127:64];
IF CMP0 = TRUE
THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] := 0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] := 0000000000000000H; FI;
DEST[MAXVL-1:128] := 0
CMPPD (128-bit Legacy SSE Version)
CMP0 := SRC1[63:0] OP3 SRC2[63:0];
CMP1 := SRC1[127:64] OP3 SRC2[127:64];
IF CMP0 = TRUE
THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] := 0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64] := 0000000000000000H; FI;
DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCMPPD __mmask8 _mm512_cmp_pd_mask( __m512d a, __m512d b, int imm);
VCMPPD __mmask8 _mm512_cmp_round_pd_mask( __m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm512_mask_cmp_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm);
VCMPPD __mmask8 _mm512_mask_cmp_round_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm256_cmp_pd_mask( __m256d a, __m256d b, int imm);
VCMPPD __mmask8 _mm256_mask_cmp_pd_mask( __mmask8 k1, __m256d a, __m256d b, int imm);
VCMPPD __mmask8 _mm_cmp_pd_mask( __m128d a, __m128d b, int imm);
VCMPPD __mmask8 _mm_mask_cmp_pd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);
VCMPPD __m256 _mm256_cmp_pd(__m256d a, __m256d b, int imm)
(V)CMPPD __m128 _mm_cmp_pd(__m128d a, __m128d b, int imm)
SIMD Floating-Point Exceptions
Invalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1, Denormal.
Other Exceptions
VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be incomplete or broken in various obvious or non-obvious ways. Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious.