VMPTRST

Store Pointer to Virtual

Opcode/Instruction	Op/En	Description
NP 0F C7 /7 VMPTRST m64	M	Stores the current VMCS pointer into memory.

Instruction Operand Encoding

Op/En	Operand 1	Operand 2	Operand 3	Operand 4
M	ModRM:r/m (w)	NA	NA	NA

Description

Stores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits and is always in memory.

Operation

IF (register operand) or (not in VMX operation) or (CR0.PE = 0) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.L = 0)
    THEN #​​​UD;
ELSIF in VMX non-root operation
    THEN VMexit;
ELSIF CPL > 0
    THEN #​​​​GP(0);
    ELSE
        64-bit in-memory destination operand := current-VMCS pointer;
        VMsucceed;
FI;

Flags Affected

See the operation section and Section 31.2.

Protected Mode Exceptions

#​​​​GP(0)	If the current privilege level is not 0.
If the memory destination operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains an unusable segment.
If the destination operand is located in a read-only data segment or any code segment.
#​PF(fault-code)	If a page fault occurs in accessing the memory destination operand.
#​​​​​SS(0)	If the memory destination operand effective address is outside the SS segment limit.
If the SS register contains an unusable segment.
#​​​UD	If operand is a register.
If not in VMX operation.

Real-Address Mode Exceptions

#​​​UD	The VMPTRST instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#​​​UD	The VMPTRST instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#​​​UD	The VMPTRST instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions

#​​​​GP(0)	If the current privilege level is not 0.
If the destination operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form.
#​PF(fault-code)	If a page fault occurs in accessing the memory destination operand.
#​​​​​SS(0)	If the destination operand is in the SS segment and the memory address is in a non-canonical form.
#​​​UD	If operand is a register.
If not in VMX operation.

This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be incomplete or broken in various obvious or non-obvious ways. Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious.