KANDW/KANDB/KANDQ/KANDD
Bitwise Logical AND Masks
| Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| VEX.L1.0F.W0 41 /r KANDW k1, k2, k3 | RVR | V/V | AVX512F | Bitwise AND 16 bits masks k2 and k3 and place result in k1. |
| VEX.L1.66.0F.W0 41 /r KANDB k1, k2, k3 | RVR | V/V | AVX512DQ | Bitwise AND 8 bits masks k2 and k3 and place result in k1. |
| VEX.L1.0F.W1 41 /r KANDQ k1, k2, k3 | RVR | V/V | AVX512BW | Bitwise AND 64 bits masks k2 and k3 and place result in k1. |
| VEX.L1.66.0F.W1 41 /r KANDD k1, k2, k3 | RVR | V/V | AVX512BW | Bitwise AND 32 bits masks k2 and k3 and place result in k1. |
Instruction Operand Encoding
| Op/En | Operand 1 | Operand 2 | Operand 3 |
|---|---|---|---|
| RVR | ModRM:reg (w) | VEX.1vvv (r) | ModRM:r/m (r, ModRM:[7:6] must be 11b) |
Description
Performs a bitwise AND between the vector mask k2 and the vector mask k3, and writes the result into vector mask k1.
Operation
KANDW
DEST[15:0] := SRC1[15:0] BITWISE AND SRC2[15:0]
DEST[MAX_KL-1:16] := 0
KANDB
DEST[7:0] := SRC1[7:0] BITWISE AND SRC2[7:0]
DEST[MAX_KL-1:8] := 0
KANDQ
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[MAX_KL-1:64] := 0
KANDD
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[MAX_KL-1:32] := 0
Intel C/C++ Compiler Intrinsic Equivalent
KANDW __mmask16 _mm512_kand(__mmask16 a, __mmask16 b);
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-63, “TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg).”
This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be incomplete or broken in various obvious or non-obvious ways. Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious.